The present invention relates to analog-to-digital converters, and more particularly to the use of an analog-to-digital converter with an offset reduction loop for detecting the presence/absence of an analog signal.
The detection of the presence/absence of analog signals is generally performed by rectifying and peak detecting an analog input signal to produce a d.c. signal. The d.c. signal is compared with a threshold value, and from the comparison the presence of the analog signal is detected. If there is no analog signal, the threshold is not exceeded, and vice versa.
Many analog signals, such as audio signals, represent zero mean value processes, i.e., over an extended period of time the direct current (d.c.) component is zero. The analog-to-digital conversion of a zero mean value signal should yield a digital signal which does not exhibit a static d.c. offset when reconstituted to analog form. This is not always true due to internal or external offsets. The sign bit of the analog-to-digital conversion output should represent the polarity of an analog sample from the analog input signal. A zero mean value input signal should yield equal numbers of positive and negative (logical 1 and 0) sign bits on average.
Examples of offset compensation circuits are shown in U.S. Pat. No. 4,965,867, issued Oct. 23, 1990 to Tsuchida et. al. entitled "Offset Compensation Circuit", and U.S. Pat. No. 4,996,529, issued Feb. 26, 1991 to Connell entitled "Auto-Zeroing Circuit for Offset Cancellation." In Tsuchida et. al. a sign bit from an ADC is integrated to generate a compensation voltage which is used to control an input filter to equalize the probability that the polarities of the sign bit are equal to each other. Connell also uses an integrator in a feedback loop to determine when the inequality of polarities of the sign bit exceeds an overflow threshold, and then provides a bias control signal that is attenuated and applied to an input limiter.